The invention relates to a sequential finite-state machine circuit, comprising a set of N bistable elements {FF(1), . . . , FF(N)} and a set of combinatory logic connected thereto, the combination of logic values of the bistable elements defining a state of the circuit which is a representation of a state of a finite-state machine, the circuit changing over to a next state at instants which are determined by a clock signal under the influence of the combinatory logic, the current state of the circuit and an input signal, the set of combinatory logic realising transitions between states of the finite-state machine in the circuit.
A circuit of this kind is known from German Offenlegungsschrift DE-3719181-A1.
The invention also relates to an integrated circuit comprising such a circuit.
A finite-state machine (FSM) is a frequently used model for the representation of logic systems. Contrary to continuous or analog machines, the operation of the FSM is based on discrete value information. FSMs can be subdivided into combinatory machines (without a memory: the input signals unambiguously define the output signals), and sequential machines (comprising a memory: the current contents thereof and the input signals unambiguously define the new contents of the memory and the output signals).
An FSM can be implemented in an FSM circuit: combinatory logic with flipflops which are retrocoupled to the logic, with input or control signals and a clock signal (synchronous FSM), the logic realising transitions between states of the FSM (represented by the contents of the flipflops) in the circuit.
An FSM may have a state which is referred to as being absorbing: this so-called rest state is reached from all feasible states, provided that the input or control signal has assumed a given series of values. The FSM is thus self-initiating: the supply of the given sequence of values of the input signal ensures that the FSM will subsequently be in the absorbing state.
When a model of such an FSM is simulated by means of a logic digital simulator, this self-initiating behavior of the circuit does not become apparent: the simulator starts with an unknown state at the beginning of the simulation and is event driven (i.e. it progresses from one state to another state), so that only the current state of the simulator is known. Due to this lack of history in the simulator, initializations via a sequence of supplied values cannot be simulated. This problem could be solved by forcing the FSM to a known state at the beginning of a simulation. However, that is not a representation of reality which should be approximated as well as possible during the simulation. Moreover, this intervention in the circuit imposes practical problems because of the difficulty in accessing internal points of the circuit.